Printed boards and printed board assemblies - Design and use - Part 5-6: Attachment (land/joint) considerations - Chip carriers with J-leads on four sides
This part of IEC 61188 provides information on land pattern geometries used for the surface attachment of electronic components with J leads on four sides. The object of this standard is to provide the appropriate size, shape and tolerances of surface mount land patterns so as to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and reworking of resulting solder joints. Each clause contains a specific set of criteria, setting out details on the component, the component dimensions, the solder joint design and the land pattern dimensions. NOTE The acronym QFJ is the naming convention used by Japan; the acronym PLCC is the naming convention used by the USA for these components.