The characterization of model parameters for semiconductor package leads has been notorious
for the lack of repeatability of modeling and of testing between sites. This lack of repeatability
has been caused less by inaccuracy of basic test instrumentation, but more by lack of uniform
conditions in test fixtures and by the diversity of methods applied. Thus, the intent for test
methodology prescribed by this guideline is to ensure the reproducibility of uniform test
conditions to be used at various test sites. As test conditions influence electrical parameter
values, they must, to a large extent, emulate the application environment in which semiconductor
devices are ultimately used.