L40 半导体分立器件综合 标准查询与下载

JEDEC JESD69A-2006 硅设备规则的信息需求

Customers utilize supplier information when performing component qualification. This information typically includes quality, reliability, electrical and mechanical performance data. In addition, customers frequently request the supplier to complete a profile, or fact sheet, on the component or component family being evaluated. This profile may include information on the materials used within the component as well as the location of the component's manufacture or test. This profile, coupled with the above mentioned data elements, support the customers' evaluation of a device's suitability for use in their application.

Information Requirements for the Qualification of Silicon Devices

DLA SMD-5962-92075 REV B-2006 硅单块 68030/40发射极耦合逻辑或晶体管-晶体管逻辑电路钟驱动器,发射极耦合逻辑,数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V).

MICROCIRCUIT, DIGITAL, ECL, 68030/40 ECL/TTL CLOCK DRIVER, MONOLITHIC SILICON

JEDEC JESD22-B117A-2006 焊接球剪切

This test method applies to solder ball shear force testing prior to end-use attachment. Solder balls are sheared individually; force and failure mode data are collected and analyzed. Both low and high speed testing are covered by this document.

Solder Ball Shear

DLA SMD-5962-97553 REV A-2006 单稳多谐振荡器晶体管硅单片电路数字双极微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, TTL, MONOSTABLE MULTIVIBRATOR, MONOLITHIC SILICON

DLA SMD-5962-86842 REV E-2006 硅单块 和门高级低功率肖脱基晶体管-晶体管逻辑电路或门,数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, ADVANCED LOWPOWER SCHOTTKY TTL, AND GATE, MONOLITHIC SILICON

DLA SMD-5962-90744 REV B-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带三态输入10比特总线或金属氧化半导体主储存器驱动器,双极互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, 10-BIT BUS/MOS MEMORY DRIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

ASTM F1892-06 半导体器件电离辐射(总剂量)效应试验的标准指南

Electronic circuits used in space, military, and nuclear power systems may be exposed to various levels of ionizing radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems. Some manufacturers currently are selling semiconductor parts with guaranteed hardness ratings. Use of this guide provides a basis for standardized qualification and acceptance testing.1.1 This guide presents background and guidelines for establishing an appropriate sequence of tests and data analysis procedures for determining the ionizing radiation (total dose) hardness of microelectronic devices for dose rates below 300 rd(SiO2)/s. These tests and analysis will be appropriate to assist in the determination of the ability of the devices under test to meet specific hardness requirements or to evaluate the parts for use in a range of radiation environments.1.2 The methods and guidelines presented will be applicable to characterization, qualification, and lot acceptance of silicon-based MOS and bipolar discrete devices and integrated circuits. They will be appropriate for treatment of the effects of electron and photon irradiation.1.3 This guide provides a framework for choosing a test sequence based on general characteristics of the parts to be tested and the radiation hardness requirements or goals for these parts.1.4 This guide provides for tradeoffs between minimizing the conservative nature of the testing method and minimizing the required testing effort.1.5 Determination of an effective and economical hardness test typically will require several kinds of decisions. A partial enumeration of the decisions that typically must be made is as follows:1.5.1 Determination of the Need to Perform Device CharacterizationFor some cases it may be more appropriate to adopt some kind of worst case testing scheme that does not require device characterization. For other cases it may be most effective to determine the effect of dose-rate on the radiation sensitivity of a device. As necessary, the appropriate level of detail of such a characterization also must be determined.1.5.2 Determination of an Effective Strategy for Minimizing the Effects of Irradiation Dose Rate on the Test ResultThe results of radiation testing on some types of devices are relatively insensitive to the dose rate of the radiation applied in the test. In contrast, many MOS devices and some bipolar devices have a significant sensitivity to dose rate. Several different strategies for managing the dose rate sensitivity of test results will be discussed.1.5.3 Choice of an Effective Test MethodologyThe selection of effective test methodologies will be discussed.1.6 Low Dose RequirementsHardness testing of MOS and bipolar microelectronic devices for the purpose of qualification or lot acceptance is not necessary when the required hardness is 100 rd(SiO2) or lower.1.7 SourcesThis guide will cover effects due to device testing using irradiation from photon sources, such as 60Co irradiators, 137Cs irradiators, and low energy (approximately 10 keV) X-ray sources. Other sources of test radiation such as linacs, Van de Graaff sources, Dymnamitrons, SEMs, and flash X-ray sources occasionally are used but are outside the scope of this guide.1.8 Displacement damage effects are outside the scope of this guide, as well.1.9 The values stated in SI units are to be regarded as the standard.

Standard Guide for Ionizing Radiation (Total Dose) Effects Testing of Semiconductor Devices

DLA SMD-5962-90939 REV C-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带倒转三态输出的八进制缓冲器和行驱动线或金属氧化半导体驱动器,双极互补金属氧化物半导体,数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, OCTAL BUFFER AND LINE DRIVER/MOS DRIVER WITH INVERTED THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-89976 REV B-2006 硅单片,结型场效应晶体管高速准确运算放大器,线性微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, LINEAR, HIGH SPEED, PRECISION, JFET, OPERATIONAL AMPLIFIER, MONOLITHIC SILICON

DLA SMD-5962-97583 REV B-2006 微型电路,数字型,双极,改进型肖特基晶体管晶体管逻辑电路,双路1/4数据选择器/多用选择器,单块硅

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS, MONOLITHIC SILICON

DLA SMD-5962-97584 REV B-2006 微型电路,数字型,双极,改进型肖特基晶体管晶体管逻辑电路,双路4输入正与非门,单块硅

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, DUAL 4-INPUT POSITIVE-NAND GATE, MONOLITHIC SILICON

DLA SMD-5962-97582 REV B-2006 微型电路,数字型,双极,改进型肖特基晶体管晶体管逻辑电路,3线到8线解码器/多用复解码器,单块硅

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS, MONOLITHIC SILICON

DLA SMD-5962-97560 REV A-2006 四重2输入阳性与门晶体管硅单片电路数字双极微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, QUAD 2-INPUT POSITIVE-OR GATES, MONOLITHIC SILICON

DLA SMD-5962-97562 REV A-2006 八角D类触发双稳态多谐振荡器晶体管硅单片电路数字双极微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS, MONOLITHIC SILICON

ASTM F72-06 半导体引线连接用金线的标准规范

1.1 This specification covers round drawn/extruded gold wire for internal semiconductor device electrical connections. Four classifications of wire are distinguished, (1) copper-modified wire, (2) beryllium-modified wire, ( 3) high-strength wire, and (4) special purpose wire. Note 1Trace metallic elements have a significant effect upon the mechanical properties and thermal stability of high-purity gold wire. It is customary in manufacturing to add controlled amounts of selected impurities to gold to modify or stabilize bonding wire properties or both. This practice is known variously as "modifying," "stabilizing," or "doping." The first two wire classifications denoted in this specification refer to wire made with either of two particular modifiers, copper or beryllium, in general use. In the third and fourth wire classifications, "high-strength" and "special purpose" wire, the identity of modifying additives is not restricted.1.2 The values stated in SI units shall be regarded as the standard.1.2.1 A mixed system of metric and inch-pound units is in widespread use for specifying semiconductor lead-bonding wire. SI-equivalent values of other commonly used units are denoted by parentheses in text and tables.The following hazard caveat pertains only to the test method portion, Section , of this specification. This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Standard Specification for Gold Wire for Semiconductor Lead Bonding

DLA SMD-5962-97581 REV A-2006 微型电路,数字型,双极,改进型肖特基晶体管晶体管逻辑电路,三路三输入正与门,单块硅

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, TRIPLE 3-INPUT POSITIVE AND GATE, MONOLITHIC SILICON

DLA SMD-5962-90746 REV B-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带三态输入八进制D型易被识破的止动销,双极互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, OCTAL D-TYPE TRANSPARENT LATCH WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-90809 REV E-2006 硅单块 操作增强器,四列微功率结型场效应晶体管直线型微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part orIdentifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, LINEAR, JFET, MICROPOWER, QUAD, OPERATIONAL AMPLIFIER, MONOLITHIC SILICON

DLA SMD-5962-97561 REV A-2006 三重3输入阳性与门晶体管硅单片电路数字双极微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, TRIPLE 3-INPUT POSITIVE AND GATES, MONOLITHIC SILICON

ASTM F458-06 金属丝连接的非破坏性抗拉试验的标准实施规范

The nondestructive wire-bond pull test provides a screen for evaluating wire-bond quality and is capable of detecting weak or nonadherent bonds. The test is not destructive to acceptable wire bonds. This practice provides a procedure for identifying a bonding situation that requires corrective action. The purpose of this practice is to identify wire bonds that may fail during subsequent screening procedures or field operation. The procedure is to be applied after bonding and before any further treatment.1.1 This practice covers nondestructive testing of individual wire bonds made by either ultrasonic, thermal compression or thermosonic techniques. The test is destructive to nonacceptable wire bonds but is designed to avoid damage to acceptable wire bonds. Note 1Common usage at the present time considers the term "wire bond" to include the entire interconnection: both welds and the intervening wire span.1.2 The practice covers wire bonds made with small-diameter (from 0.0007 to 0.003-in. (18 to 76-m)) wire of the type used in integrated circuits and hybrid microcircuits.1.3 This practice can be used only when the loop height of the wire bond is large enough to allow a suitable hook for pulling to be placed under the wire.1.4 While the procedure is applicable to wire of any composition and metallurgical state, criteria are given only for gold and aluminum wire.1.5 A destructive pull test is used on wire bonds of the same type and geometry to provide the basis for the determination of the nondestructive pulling force to be used in this practice. This may only be used if the sample standard deviation, s, of the pulling forces required to destroy at least 25 of the same wire bonds tested by the destructive pull-test method is less than or equal to 0.25 of the sample average, x. If s > 0.25 x, this practice may not be used. Note 2If s > 0.25 x, some aspect of the bonding process is out of control. Following corrective action, the destructive pull-test measurements should be repeated to determine if the s 0.25 xcriterion is met.1.6 The nondestructive wire-bond pull test is to be performed before any other treatment or screening following bonding and at the same point in processing as the accompanying destructive test. Preferably, this is done immediately after bonding.1.7 The procedure does not ensure against wire-bond failure modes induced after the test has been performed.1.8 The values stated in inch-pound units are to be regarded as the standard. The values given in parentheses are for information only.This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Standard Practice for Nondestructive Pull Testing of Wire Bonds