As stated in the introduction, the scope of the DPCS standard is to make it possible for integrated circuit
designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated
circuit vendors to express timing and power information once (for a given technology), and for EDA
vendors to meet their application performance and capacity needs. The intended use for these standards is
integrated circuit timing and power. The standard may be applied to both unit logic cells supplied by the
integrated circuit vendor and logical macros defined by the integrated circuit designer. Although this specification
is written towards the integrated circuit supplier and EDA developer, its application applies equally
well to representation of timing and power for designer defined macros (or hierarchical design elements).
These specifications make it possible to achieve consistent timing and power results, but do not guarantee it.
They provide for a single executable software program which computes delay and power based on integrated
circuit vendor-supplied algorithms (or designer-supplied algorithms for macros), but does not guarantee
EDA applications correctly communicate the design-specific information required for these algorithms. By
specifying standard exchange formats for parasitic data and floorplanning information, the standard provides
a marked improvement over design environments with no such standards. However, it is the responsibility of
the EDA application to correctly correlate the information between these standard exchange files and the
actual design. These specifications also do not detail how the information contained within the standard
exchange files shall be obtained.