IEC 61523-1:2001
延迟和电力计算标准 第1部分：集成电路延迟系统和电力计算系统

Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems

被代替

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标准号

IEC 61523-1:2001

发布

2001年

发布单位

国际电工委员会

替代标准

IEC 61523-1:2012*IEEE Std 1481

当前最新

IEC 61523-1:2012*IEEE Std 1481

 

 

适用范围

As stated in the introduction, the scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs. The intended use for these standards is integrated circuit timing and power. The standard may be applied to both unit logic cells supplied by the integrated circuit vendor and logical macros defined by the integrated circuit designer. Although this specification is written towards the integrated circuit supplier and EDA developer, its application applies equally well to representation of timing and power for designer defined macros (or hierarchical design elements). These specifications make it possible to achieve consistent timing and power results, but do not guarantee it. They provide for a single executable software program which computes delay and power based on integrated circuit vendor-supplied algorithms (or designer-supplied algorithms for macros), but does not guarantee EDA applications correctly communicate the design-specific information required for these algorithms. By specifying standard exchange formats for parasitic data and floorplanning information, the standard provides a marked improvement over design environments with no such standards. However, it is the responsibility of the EDA application to correctly correlate the information between these standard exchange files and the actual design. These specifications also do not detail how the information contained within the standard exchange files shall be obtained.

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