JEDEC JEP122C-2006
硅半导体器件的故障机制和模式

Failure Mechanisms and Models for Silicon Semiconductor Devices


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标准号
JEDEC JEP122C-2006
发布日期
2006年03月01日
实施日期
废止日期
中国标准分类号
L40
国际标准分类号
31.080
发布单位
(美国)固态技术协会,隶属EIA
适用范围
Accelerated tests are typically used to find and identify potential failure mechanisms in semiconductor devices and to estimate the rate of their occurrence in electronic systems. The historical approach to investigating the relationship between a maximum stress failure rate and a system failure rate is to choose a single representative "equivalent" thermal activation energy for a given product or product group. A single, best-estimate activation energy value facilitates accurate estimation of the acceleration factor for the device failure-rate estimation in the system application. While that approach has been generally accepted by the industry because of its simplicity and direct relationship to products, another method has been developed, the Sum-of-the-Failure-Rates method, that offers more knowledge of why devices fail.




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