This procedure is intended for VNA (Vector Network Analyzer) based measurement of pin input capacitance for devices with SSTL (Stub Series Terminated Logic) interface . This procedure does not mandate a specific method for measuring input capacitance. It has only to be considered mandatory if it is explicitly refered to by a component specification in conjunction with a value of an input capacitance defined in such a specification.
JEDEC JEP147-2003由(美国)固态技术协会,隶属EIA US-JEDEC 发布于 2003。
JEDEC JEP147-2003 在中国标准分类中归属于: L33 电子设备专用微特电机。
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