JEDEC JESD22-B106D-2008
通孔安装装置用焊料冲击阻力

Resistance to Solder Shock for Through-Hole Mounted Devices


JEDEC JESD22-B106D-2008 发布历史

This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. This test method shall not be used to simulate wave soldering of surface mount device packages that are glued onto the same side of the board as the solder wave and are fully submerged into the solder wave. The test method for simulating SMT devices through the wave is JESD22- A111, "Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices". In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure will determine whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor.

JEDEC JESD22-B106D-2008由(美国)固态技术协会,隶属EIA US-JEDEC 发布于 2008-04-01。

JEDEC JESD22-B106D-2008 在中国标准分类中归属于: J33 焊接与切割。

JEDEC JESD22-B106D-2008的历代版本如下:

JEDEC JESD22-B106D-2008 通孔安装装置用焊料冲击阻力 由 JEDEC JESD22-B106C-2005 变更而来。

 

 

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标准号
JEDEC JESD22-B106D-2008
发布日期
2008年04月01日
实施日期
废止日期
中国标准分类号
J33
发布单位
US-JEDEC
被代替标准
JEDEC JESD22-B106C-2005
适用范围
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. This test method shall not be used to simulate wave soldering of surface mount device packages that are glued onto the same side of the board as the solder wave and are fully submerged into the solder wave. The test method for simulating SMT devices through the wave is JESD22- A111, "Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices". In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure will determine whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor.




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