L40 半导体分立器件综合 标准查询与下载

DLA SMD-5962-87656 REV B-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,明确八进制D型双稳态多谐振荡器触发器,高速互补金属氧化物半导体,数字微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, FAST CMOS, OCTAL D-TYPE FLIP-FLOP WITH CLEAR, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-87560 REV F-2006 硅单块 晶体管-晶体管逻辑电路到发射极耦合逻辑的翻译,数字微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, TTL-TO-ECL TRANSLATOR, MONOLITHIC SILICON

DLA SMD-5962-90748 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带倒转三态输入八进制缓冲器和行驱动线,双极互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, OCTAL BUFFER AND LINE DRIVER WITH INVERTING THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-90743 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带三态输入八进制缓冲器和行驱动线,双极互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, OCTAL BUFFER AND LINE DRIVER WITH THREESTATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-90742 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带倒转三态输入八进制缓冲器和行驱动线,双极互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR CMOS, OCTAL BUFFER AND LINE DRIVER WITH INVERTING THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

KS C IEC 60749-34:2006 半导体器件.机械和环境测试方法.第34部分:电力循环

이 시험 방법은 반도체 내부 다이 및 내부 커넥터에서 소비하는 전력의 사이클링으 로 인한

Semiconductor devices-Mechanical and climatic test methods-Part 34:Power cycling

KS C IEC 60749-23:2006 半导体器件.机械和气候试验方法.第23部分:高温操作寿命

이 시험은 시간이 지남에 따라 바이어스 조건과 온도가 고체 상태 소자에 미치는 영향을 알아

Semiconductor devices－Mechanical and climatic test methods－Part 23：High temperature operating life

DLA SMD-5962-96581 REV B-2006 抗辐射数字的互补金属氧化物半导体,四重S-R闭锁装置,晶体管兼容输入硅单片电路线型微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V).

MICROCIRCUIT, DIGITAL, RADIATION HARDENED, ADVANCED CMOS, QUADRUPLE S-R LATCH, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

BS EN 62258-1:2005 半导体压模制品.第1部分:采购和使用要求

This part of IEC 62258 has been developed to facilitate the production, supply and use of semiconductor die products, including – wafers, – singulated bare die, – die and wafers with attached connection structures, – minimally or partially encapsulated die and wafers. This standard defines the minimum requirements for the data which are needed to describe such die products and is intended as an aid in the design of and procurement of assemblies incorporating die products. It covers the requirements for data, including – product identity, – product data, – die mechanical information, – test, quality, assembly and reliability information, – handling, shipping and storage information. This standard covers the specific requirements for data needed to describe the geometrical properties of die, their physical properties and the means of connection necessary for their use in the development and manufacture of products. It also contains, in Annexes A and B, terminology and a list of common acronyms, respectively.

Semiconductor die products - Part 1: Requirements for procurement and use

DLA SMD-5962-87508 REV E-2006 硅单块 发射极耦合逻辑到晶体管-晶体管逻辑电路的翻译,数字微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, ECL-TO-TTL TRANSLATOR, MONOLITHIC SILICON

JEDEC JEP122C-2006 硅半导体器件的故障机制和模式

Accelerated tests are typically used to find and identify potential failure mechanisms in semiconductor devices and to estimate the rate of their occurrence in electronic systems. The historical approach to investigating the relationship between a maximum stress failure rate and a system failure rate is to choose a single representative "equivalent" thermal activation energy for a given product or product group. A single, best-estimate activation energy value facilitates accurate estimation of the acceleration factor for the device failure-rate estimation in the system application. While that approach has been generally accepted by the industry because of its simplicity and direct relationship to products, another method has been developed, the Sum-of-the-Failure-Rates method, that offers more knowledge of why devices fail.

Failure Mechanisms and Models for Silicon Semiconductor Devices

JEDEC JESD22-B113-2006 手持电子产品元件互联可靠性特征的桌子高度交变弯曲测试方法

The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.

Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products

JEITA EDR7315B-2006 半导体包装件球栅阵列(BGA)用设计指南

This Design guide for semiconductor packages defines the general outline drawings, dimensions and tolerances for square-body packages of Plastic Ball Grid Array (P-BG, A), Tape Ball Grid Array (T-BGA) and Ceramic Ball Grid Array (C-BGA), which are categorized as Form-D in the Recommended Practice on Standard for the Preparation of Qutline Drawings of Semiconductor Packages, JF_ITA ~D-7300, with a terminal pitch of 1.0 mm and higher.

Design guide for semiconductor packages ball grid array(BGA)

IEC 60191-2:1966/AMD12:2006 半导体器件的机械标准化.第2部分:尺寸.修改件12

This is Amendment 12 to IEC 60191-2-2006 (Mechanical standardization of semiconductor devices - Part 2: Dimensions)

Mechanical standardization of semiconductor devices - Part 2: Dimensions; Amendment 12

DLA SMD-5962-90758 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,双2比特双稳定易被识破的止动销,高速互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, DUAL 2-BIT BISTABLE TRANSPARENT LATCH, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-90848 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,可预设置的同步4比特二进制升值或降值计数器,高速互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V).

MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, PRESETTABLE SYNCHRONOUS 4-BIT BINARY UP/DOWN COUNTER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-86890 REV C-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,八进制施米特触发器高速互补金属氧化物半导体,数字微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, HEX SCHMITT TRIGGER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-87725 REV B-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,带主重设置八进制D型双稳态多谐振荡器触发电路,高速互补金属氧化物半导体,数字微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL D-TYPE FLIP-FLOP WITH MASTER RESET, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-90703 REV A-2006 硅单块 晶体管-晶体管逻辑电路兼容输入,四列2输入非倒转多路复用器,高速互补金属氧化物半导体数字微型电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, QUAD 2-INPUT INVERTING MULTIPLEXER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON

DLA SMD-5962-86881 REV B-2006 硅单块 算术逻辑部件低功率肖脱基晶体管-晶体管逻辑电路 数字主储存器微型电路

This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.

MICROCIRCUIT, DIGITAL, LOW POWER SCHOTTKY TTL, ARITHMETIC LOGIC UNIT, MONOLITHIC SILICON