L40 半导体分立器件综合 标准查询与下载

DLA SMD-5962-97553 REV A-2006 单稳多谐振荡器晶体管硅单片电路数字双极微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

MICROCIRCUIT, DIGITAL, BIPOLAR, TTL, MONOSTABLE MULTIVIBRATOR, MONOLITHIC SILICON

ASTM F458-06 金属丝连接的非破坏性抗拉试验的标准实施规范

The nondestructive wire-bond pull test provides a screen for evaluating wire-bond quality and is capable of detecting weak or nonadherent bonds. The test is not destructive to acceptable wire bonds. This practice provides a procedure for identifying a bonding situation that requires corrective action. The purpose of this practice is to identify wire bonds that may fail during subsequent screening procedures or field operation. The procedure is to be applied after bonding and before any further treatment.1.1 This practice covers nondestructive testing of individual wire bonds made by either ultrasonic, thermal compression or thermosonic techniques. The test is destructive to nonacceptable wire bonds but is designed to avoid damage to acceptable wire bonds. Note 1Common usage at the present time considers the term "wire bond" to include the entire interconnection: both welds and the intervening wire span.1.2 The practice covers wire bonds made with small-diameter (from 0.0007 to 0.003-in. (18 to 76-m)) wire of the type used in integrated circuits and hybrid microcircuits.1.3 This practice can be used only when the loop height of the wire bond is large enough to allow a suitable hook for pulling to be placed under the wire.1.4 While the procedure is applicable to wire of any composition and metallurgical state, criteria are given only for gold and aluminum wire.1.5 A destructive pull test is used on wire bonds of the same type and geometry to provide the basis for the determination of the nondestructive pulling force to be used in this practice. This may only be used if the sample standard deviation, s, of the pulling forces required to destroy at least 25 of the same wire bonds tested by the destructive pull-test method is less than or equal to 0.25 of the sample average, x. If s > 0.25 x, this practice may not be used. Note 2If s > 0.25 x, some aspect of the bonding process is out of control. Following corrective action, the destructive pull-test measurements should be repeated to determine if the s 0.25 xcriterion is met.1.6 The nondestructive wire-bond pull test is to be performed before any other treatment or screening following bonding and at the same point in processing as the accompanying destructive test. Preferably, this is done immediately after bonding.1.7 The procedure does not ensure against wire-bond failure modes induced after the test has been performed.1.8 The values stated in inch-pound units are to be regarded as the standard. The values given in parentheses are for information only.This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Standard Practice for Nondestructive Pull Testing of Wire Bonds

ASTM F72-06 半导体引线连接用金线的标准规范

1.1 This specification covers round drawn/extruded gold wire for internal semiconductor device electrical connections. Four classifications of wire are distinguished, (1) copper-modified wire, (2) beryllium-modified wire, ( 3) high-strength wire, and (4) special purpose wire. Note 1Trace metallic elements have a significant effect upon the mechanical properties and thermal stability of high-purity gold wire. It is customary in manufacturing to add controlled amounts of selected impurities to gold to modify or stabilize bonding wire properties or both. This practice is known variously as "modifying," "stabilizing," or "doping." The first two wire classifications denoted in this specification refer to wire made with either of two particular modifiers, copper or beryllium, in general use. In the third and fourth wire classifications, "high-strength" and "special purpose" wire, the identity of modifying additives is not restricted.1.2 The values stated in SI units shall be regarded as the standard.1.2.1 A mixed system of metric and inch-pound units is in widespread use for specifying semiconductor lead-bonding wire. SI-equivalent values of other commonly used units are denoted by parentheses in text and tables.The following hazard caveat pertains only to the test method portion, Section , of this specification. This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

Standard Specification for Gold Wire for Semiconductor Lead Bonding

DLA SMD-5962-95574 REV A-2006 双极晶体管四倍2输入阳性硅单片电路线型微电路

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V).

MICROCIRCUIT, DIGITAL, BIPOLAR, TTL QUADRUPLE 2-INPUT POSITIVE-OR GATE, MONOLITHIC SILICON

KS C IEC 60749-20:2005 半导体器件.机械和气候试验方法.第20部分:SMDs塑料囊状物抗湿气和焊接热的综合影响

이 규격은 반도체 소자(개별 소자 및 집적 회로)에 적용된다. 이 시험은 플라스틱 으로 캡

Semiconductor devices－Mechanical and climatic test methods－ Part 20：Resistance of plastic-encapsulated SMDs to the combined effect of moisture and soldering heat

KS C IEC 60749-21:2005 半导体器件.机械和气候试验方法.第21部分:可焊性

이 규격은 부착용 주석-납(SnPb) 또는 무연납(Pb-free)의 땜납을 이용하여 다른

Semiconductor devices－Mechanical and climatic test methods－ Part 21：Solderability

KS C IEC 60749-19:2005 半导体器件.机械和气候试验方法.第19部分:模剪切强度试验

이 규격은 반도체 다이 또는 패키지 수동 부품을 패키지 헤더나 다른 기판에 부착하는 데 사

Semiconductor devices－Mechanical and climatic test methods－Part 19：Die shear strength

JIS C 0807:2005 使用条形码和二维符号的电子元器件用产品包装标签

この規格は，自動実装用の電子及び電気部品の容器包装ラべルに適用する。これらのラべルには，バーコード(一次元シンボル)及び二次元(2D)シンポルを使用する。ただし，電子及び電気部品本体へのラべル表示及び出荷用のラべル表示には，この規格を適用しない。また，小売の販売ルートで用いる電子及び電気部品の容器包装ラべルにも，この規格を適用しない。一般に，バーコード及び二次元シンボルは，電子機器の自動実装組立てラインにおける自動識別及び自動実装用に使用される。所期の目的には，生産ラインの容器包装，在庫及び内部流通の管理を自動化するシステムを含んでいる備考この規格の対応国際規格を，次に示す。なお，対応の程度を表す記号は，ISO/IEC Guide 21に基づき， IDT(一致している)，MOD（修正している），NEQ(同等でない)とする。IEC 62090:2002 . Product package labels for electronic components using bar code and two-dimensional symbologies (IDT）

Product package labels for electronic components using bar code and two-dimensional symbologies

BS PD CLC/TR 62258-3:2007 半导体压模产品.第3部分:搬运、包装和储存的良好规范建议

This technical report has been developed to facilitate the production, supply and use of semiconductor die products, including: – wafers, – singulated bare die, – die and wafers with attached connection structures, and – minimally or partially encapsulated die and wafers. This report contains suggested good practice for the handling, packing and storage of die products. Success in manufacture of electronic assemblies containing die products is enhanced by attention to handling, storage and environmental conditions. This report provides guidelines taken from industry experience and is especially useful to those integrating die products into assemblies for the first time. It is also intended as an aid to setting up and auditing facilities that handle or use bare die products, from wafer fabrication to final assembly.

Semiconductor die products — Part 3: Recommendations for good practice in handling, packing and storage

BS EN 60749-21:2005 半导体器件.机械和气候试验方法.软钎焊性

This part of IEC 60749 establishes a standard procedure for determining the solderability of device package terminations that are intended to be joined to another surface using tin-lead (SnPb) or lead-free (Pb-free) solder for the attachment. This test method provides a procedure for ‘dip and look’ solderability testing of through hole, axial and surface mount devices (SMDs) as well as an optional procedure for a board mounting solderability test for SMDs for the purpose of allowing simulation of the soldering process to be used in the device application. The test method also provides optional conditions for ageing. This test is considered destructive unless otherwise detailed in the relevant specification.

Semiconductor devices - Mechanical and climatic test methods - Solderability

NF C96-022-21:2005 半导体器件.机械和气候试验方法.第21部分:软焊性

Semiconductor devices - Mechanical and climatic test methods - Part 21 : solderability.

NF C96-022-34:2005 半导体器件.机械和气候试验方法.第34部分:电力循环

Semiconducteur devices - Mechanical and climatic test methods - Part 34 : power cycling.

IEC 60749-33:2005 半导体器件.机械和气候试验方法.第33部分:加速抗湿.无偏压热器

The unbiased autoclave test is performed to evaluate the moisture resistance integrity of non-hermetically packaged solid-state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test which employs cond

Semiconductor devices - Mechanical and climatic test methods - Part 33: Accelerated moisture resistance - Unbiased autoclave

IEC 60749-34:2005 半导体器件.机械和气候试验方法.第34部分:电力循环

Used to determine the resistance of a semiconductor device to thermal and mechanical stresses due to cycling the power dissipation of the internal semiconductor die and internal connectors. This happens when low-voltage operating biases for forward condu

Semiconductor devices - Mechanical and climatic test methods - Part 34: Power cycling

BS EN 62258-2:2005 半导体压模制品.交换数据格式

This part of IEC 62258 has been developed to facilitate the production, supply and use of semiconductor die products, including but not limited to – wafers, – singulated bare die, – die and wafers with attached connection structures, – minimally or partially encapsulated die and wafers. This standard specifies the data formats that may be used for the exchange of data covered by other parts in the IEC 62258 series as well as definitions of all parameters used according to the principles and methods of IEC 61360-1, IEC 61360-2 and IEC 61360-4. It introduces a Device Data Exchange (DDX) format, with the prime goal of facilitating the transfer of adequate geometric data between the die manufacturer and the CAD/CAE user and formal information models that allow data exchange in other formats such as STEP physical file format, fin accordance with ISO 10303-21 and XML. The data format has been kept intentionally flexible to permit usage beyond this initial scope. This standard reflects the DDX data format: version 1.2.1.

Semiconductor die products - Exchange data formats

GJB 548B-2005 微电子器件试验方法和程序

本标准规定了军用微电子器件的环境、机械、电气试验方法和试验程序，以及为保证微电子器件满足预定用途所要求的质量和可靠性而必须的控制和限制措施。 本标准适用于军用及空间应用的微电子器件。 如果承制方标明或声称其半导体集成电路符合本标准的规定，则必须满足方法5004、5005或5010（对复杂微电路）的要求，混合集成电路应满足GJB 2438的要求，同时应满足本标准的一般要求和所引用的其他试验方法的要求，而且产品规范应经标准化机构确认。

Test methods and procedures for microelectronic device

IEC 60749-21:2005 半导体器件.机械和气候试验方法.第21部分:可焊性

Establishes a standard procedure for determining the solderability of device package terminations that are intended to be joined to another surface using tin-lead or lead-free solder for the attachment. Provides a procedure for 'dip and look' solderabili

Semiconductor devices - Mechanical and climatic test methods - Part 21: Solderability

DLA SMD-5962-96665 REV D-2005 抗辐射互补金属氧化物半导体晶体管对互补金属氧化物半导体,或互补金属氧化物半导体对互补金属氧化物半导体电压转换机构,硅单片电路数字微电路

This drawing documents three product assurance class levels consisting of high reliability (device classes Q andM), space application (device class V) and for appropriate satellite and similar applications (device class T). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class T, the user is encouraged to review the manufacturer’s Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended application.

MICROCIRCUIT, DIGITAL, RADIATION HARDENED, CMOS, HEX VOLTAGE LEVEL SHIFTER FOR TTL-TO-CMOS OR CMOS-TO- CMOS OPERATION, MONOLITHIC SILICON

IEC 62047-1:2005 半导体装置.微型机电装置.第1部分:术语和定义

This part of IEC 62047 defines terms for micro-electromechanical devices including the process of production of such devices.

Semiconductor devices - Micro-electromechanical devices - Part 1: Terms and definitions

DLA SMD-5962-03247 REV B-2005 双信道光耦合器金属氧化物半导体场效应晶体管电源的线性混合微型电路

This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN.

MICROCIRCUIT, HYBRID, LINEAR, POWER MOSFET, DUAL CHANNEL, OPTOCOUPLER