35.160 微处理机系统 标准查询与下载

DB43/T 1777.1-2020 信息技术应用创新工程建设规范 第1部分：台式微型计算机通用技术要求

Construction Specifications for Information Technology Application Innovation Projects Part 1: General Technical Requirements for Desktop Microcomputers

DB43/T 1777.3-2020 信息技术应用创新工程建设规范 第3部分：服务器通用技术要求

Information Technology Application Innovation Project Construction Specifications Part 3: General Technical Requirements for Servers

DB43/T 1777.2-2020 信息技术应用创新工程建设规范 第2部分：便携式微型计算机通用技术要求

Information Technology Application Innovation Project Construction Specifications Part 2: General Technical Requirements for Portable Microcomputers

T/CCZX 6-2019 不间断电源

本标准规定了不间断电源（以下简称：UPS）的术语和定义、缩略语、分类、技术要求、试验方法、检验规则、标志、使用说明书、包装运输、贮存等方面信息。

ups

BS EN 50672:2017 计算机和计算机服务器的生态设计要求

What is BS EN 50672 - Ecodesign of computers and servers about?    BS EN 50672 focuses on Ecodesign requirements for computers and computer servers. BS EN 50672 applies to desktop computers, integrated desktop computers, notebook computers (including tablet computers, slate computers, and mobile thin clients), desktop thin clients, workstations, mobile workstations, small-scale servers and computer servers, that can be powered directly from the mains alternating current, including via an external or internal power supply.   BS EN 50672 provides methods to determine:   The energy consumption of desktop computers, integrated desktop comput...

Ecodesign requirements for computers and computer servers

EN 50672:2017 计算机和计算机服务器的生态设计要求

Ecodesign requirements for computers and computer servers

GSO ISO/IEC 13213:2017 信息技术 微处理器系统 微型计算机总线的控制和状态寄存器（CSR）架构

This clause summarizes the feature sets provided by the CSR Architecture and illustrates how these features are expected to be used. The CSR Architecture supports the concept of bus bridges, which (after being prop- erly initialized) can transparently forward transactions from one compliant bus to another. This simplifies software development and encourages the use of specialized (low-cost or high-performance) bus standards. By defining a common CSR Architecture for multiple buses, the amount of customized software necessary to support each bus standard is minimized. To improve the amount of software transparency in such multiple -bus configurations, the scope of the CSR specification includes the following: a) Physical Address Space Partitions. The partitioning of the address space between node CSRs and memory is defined. Both 32 -bit and 64 -bit addressing options are allowed. b) Common Transaction Sets. A common transaction set (including error -status codes) is defined. This transaction set can be transparently passed through bridges. c) Core CSRs. The location and meaning of the core CSRs, which are accessed during the system ini- tialization process, are defined. This provides a uniform software interface, independent of the phys- ical bus location. d) 1D -ROM. The format and meaning of the node's ROM data structures are defined. The ROM direc- tory structure supports standard and vendor -dependent data types. e) Interrupts. Standard target addresses are provided for interrupts that are broadcast on the bus to all nodes, or broadcast within the node (nodecast) to multiple units. Other vendor -dependent quadlet registers may be provided for interrupts that are directed to individual units. f) Messages. Standard target addresses are provided for messages that can be broadcast or nodecast to multiple nodes. Other vendor -dependent registers may be provided for messages that are directed to individual units

Information technology -- Microprocessor systems -- Control and Status Registers (CSR) Architecture for microcomputer buses

GSO IEC 62623:2017 台式机和笔记本电脑 能耗测量

This International Standard covers personal computing products. It applies to desktop and notebook computers as defined in 4.1 that are marketed as final products and that are hereafter referred to as the equipment under test (EUT) or product. This standard specifies: – a test procedure to enable the measurement of the power and/or energy consumption in each of the EUT's power modes; – formulas for calculating the typical energy consumption (TEC) for a given period (normally annual); – a majority profile that should be used with this standard which enables conversion of average power into energy within the TEC formulas; – a system of categorisation enabling like for like comparisons of energy consumption between EUTs; – a pre-defined format for the presentation of results. This standard does not set any pass/fail criteria for the EUTs. Users of the test results should define such criteria.

Desktop and notebook computers - Measurement of energy consumption

T/ZZB 0210-2017 电子计算器

本标准规定了电子计算器的基本要求、技术要求、试验方法、检验规则、标志、包装、运输、贮存及质量保证。 本标准适用于采用电池或太阳能供电、液晶显示，具有语音、多模式、时钟功能的电子计算器（以下简称计算器）。

Electronic calculators

SJ/T 11720-2018 高性能计算机 刀片式服务器 计算刀片机械技术要求

High performance computer blade server computing blade mechanical technical requirements

GSO IEC 824:2016 与微处理器相关的术语

This standard gives terms and definitions applicable to microprocessor systems.

Terminology related to microprocessors

SJ/T 11653-2016 电子收款机通用规范

General specifications for electronic cash registers

SJ/T 11536.1-2015 高性能计算机 刀片服务器 第1部分:管理模块技术要求

SJ/T 11536的本部分规定了刀片服务器管理模块的功能特性和对其他模块的监控要求。 本部分适用于刀片服务器管理模块的设计、开发与测试等。

High performance computer.Blade server.Part 1: Technical requirement for management module

SJ/T 11537-2015 高性能计算机 机群 监控系统技术要求

本标准规定了高性能计算机机群监控系统的技术要求，包括机群监控系统结构、系统功能、性能要求和数据接口定义。 本标准适用于高性能计算机机群监控系统设计、开发，以及机群系统的维护。

High performance computer.Cluster.Technical requirement for monitoring system

GSO ISO/IEC 10861:2015 信息技术 微处理器系统 高性能 32 位同步总线：Multibus 2

This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. a) This standard defines a high-performance 32-bit synchronous bus standard. b) The bus standard must have a design-in lifetime of 10 years with backward compatibility. c) The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time. d) The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 1 297-3, and 603-2) with recognition of the need for special front panels to address ESD,EMI, and RFI requirements. e) Options within the standard will be clearly identified. f) The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system. g) The standard is intended to support heterogeneous processor types in the same system. h) Message-passing format and protocol is intended for future migration to a serial system bus.

Information technology -- Microprocessor systems -- High-performance synchronous 32-bit bus: MULTIBUS II

GSO ISO/IEC 11458:2015 信息技术 微处理器系统 VICbus 箱间电缆总线

The widespread use of high-performance, multi-processor systems based on backplane buses such as the IEC 821 bus (VMEbus), has inevitably led to the requirement to create multi-crate (-subrack, -chassis, etc.) systems. The VICbus inter-crate cable bus is designed to achieve such assemblies in a standard way. VICbus, a multiplexed, multi-master, multi-slave cable bus, connects multiple backplane buses or stand-alone devices, providing transparent, softwareless interconnection for low latency short data transactions and fast transmission of data blocks over cables of up to 100 m in length. Address and data signals, each of 32 bits, together with those necessary for the control of the bus protocols, signal multiplexing, reset and error reporting are transmitted on twisted-wire pairs using differential line drivers and receivers. Up to 31 devices are permitted on a single VICbus cable. VICbus data transfer protocols include both a compelled mode with end-to-end acknowledgement as well as two, high speed, non-compelled modes for high rate data transfers. The compelled protocols allow both broadcast (master write) and broadcall (master read) data transfers. One of the noncompelled protocols allows broadcast transfers, whereas neither permit broadcall operation. Inter-master arbitration uses an efficient, modified single-level, daisy-chained mechanism. The interrupt mechanism allows 32 interrupt requests, multiplexed on eight physical lines. The specification includes system failure reporting, reset and live connection and disconnection, as well as the specification of control and status registers. Particular attention has been paid to redundancy of operation. Whilst VICbus has been derived with multi-crate backplane bus systems in mind, this specification does not preclude the design of stand-alone VICbus devices. A normative annex giving rules and recommendations for a VMEbus to VICbus interface has been included, and further, similar annexes for other backplane bus standards will be added as the need arises.

Information technology -- Microprocessor systems -- VICbus -- Inter-crate cable bus

GSO ISO/IEC 13961:2015 信息技术 可扩展一致性接口（SCI）

This standard will encompass two levels of interface, defining operation over distances less than 10 m. The physical layer will specify electrical, mechanical, and thermal characteristics of connectors and cards. The logical level will describe the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives, control and status registers, and initialization and error recovery facilities. The preceding statements were those submitted to and approved by the IEEE Standards Board as the definition of the SCI project. These goals have been met and exceeded: support for message-passing was added, and the operating distance is not limited to 10 m. (The intent of that limitation was to make clear that this is not yet-another Local Area Network.) The real distinction between SCI and a network has more to do with the memory-access-based model SCI uses and the distributed cache-coherence model. The practical operating distance depends more on the throughput and performance needed than on any absolute limit built into the specification. Very long links would yield unacceptable performance for many users (but perhaps not all). In particular, the fibre-optic physical layer can extend the SCI paradigm over distances long enough to link a computer to its I/O devices, or to link several nearby processors. No arbitrary length limit would be appropriate, but practical considerations including the throughput requirements and the cost of transmitters and receivers will set the lengths that people consider useful. A very-high-priority goal was that SCI be cost-effective for small systems as well as for the massively parallel ones mentioned in the purpose statement above. SCI's low pin count and simple ring implementation make medium-performance, few-processor systems easier to build with SCI than with bused backplane systems; a two-layer backplane should be sufficient, and three layers should be enough to support the optional geographical addressing mechanism. The SCI interface, complete with transceivers, fits into a single IC package that includes much of the logic needed to support the cache-coherence protocols. This economy for small systems leads to the expectation that SCI processor boards will be built in high volume, making them inexpensive enough to be assembled in large numbers for building supercomputers at low cost. SCI also simplifies the construction of reliable systems. SCI Type 1 modules are well protected against electrostatic discharge and electromagnetic interference, and can be safely inserted while the remainder of the system remains powered. SCI supports live insertion and withdrawal by using a single supply voltage (with on-board conversion as needed) and staggered pin lengths in the connector to guarantee safe sequencing. Note, however, that system software plays an important role in live insertion or removal of a module because the resources provided by that module have to be allocated and deallocated appropriately. In systems where several modules share a ringlet, the removal of one module interrupts all communication via that ringlet, so the resources on those modules also have to be deallocated. A similar situation arises in any system that may have multiple processors resident on one field-replaceable board: all have to be deallocated when any one is replaced. The system software for handling the deallocation and reallocation of these resources is outside SCI's scope. Although SCI does not provide fault tolerance directly in its low-level protocols, it does provide the support needed for implementing fault-tolerant operation in software. With this recovery software, the SCI coherence protocols are robust and can recover from an arbitrary number of detected transmission failures (packets that are lost or corrupted). The SCI paradigm removes the limits that bus structures place on throughput, but its latency is of course limited by the speed of signal propagation (less than the speed of light). Ever-increasing throughput can be expected as technology improves, but the organization of hardware and software will have to take into account the relatively constant latency (delay between request and response), which is proportional to the physical size of the system. The last generation of buses approached the ultimate limits of performance, leading to the concept of an ultimate standard. However, the initially defined SCI physical layers are likely just the first of a series of implementations having higher or lower performance levels. The 1 Gbyte/s link speed specified for the initial ECL/copper-backplane implementation was chosen based on a combination of marketing and engineering considerations. From a marketing point of view, it was necessary to define a territory that did not disturb the markets for present 32-bit standards or present networks, and from an engineering point of view this link speed was near the edge of what available signalling technology and integrated circuit technology could support. New technologies, such as better cables, connectors, transceivers; IC packages with more pins or higher power-dissipation capabilities; or faster ICs, could make it practical or desirable to implement SCI on new physical-layer standards. Such standards, with different link widths or bit rates, will be developed from time to time. However, packet formats and higher level coherence protocols will be the same across all these physical implementations. That should make the problem of interfacing one SCI system to another relatively simple – SCI already includes the necessary mechanisms to cope easily with speed differences.

Information technology -- Scalable Coherent Interface (SCI)

GSO ISO/IEC 14575:2014 信息技术 微处理器系统 异构互连 (HIC)（用于并行系统构建的低成本、低延迟可扩展串行互连）

This International Standard applies to physical connectors and cables, electrical properties, and logical protocols for point-to-point serial scalable interconnect, operating at speeds of 10 Mbit/s to 200 Mbit/s and at 1 Gbit/s in copper and optic technologies (as developed in Open Microprocessor Systems Initiative/Heterogeneous InterConnect Project (OMI/HIC)). The object of this International Standard is to enable high-performance, scalable, modular, parallel systems to be constructed with low system integration cost; to support communications systems fabric; to provide a transparent implementation of a range of high-level protocols (communications, e.g. ATM, message passing, shared memory transactions, etc.), and to support links between heterogeneous systems.

Information technology -- Microprocessor systems -- Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)

GSO ISO/IEC 14576:2014 信息技术 -同步总线系统 -逻辑层

This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently. The contents given in this specifications are as follows: a) System bus interface signal provisions; b) Bus operations and transfer protocol for each bus operation; c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system; d) Fault detection function using parity check and duplex configuration for control signals.

Information technology -- Synchronous Split Transfer Type System Bus (STbus) -- Logical Layer

JIS C 62623:2014 台式机和笔记本电脑. 能耗的测量

Desktop and notebook computers -- Measurement of energy consumption